The invention relates to an FM demodulator having DC offset compensation. In particular, the invention is suited for use in an FM radio system of the kind in which the intermediate frequency (IF) strip of the digital FM radio circuit is tuned to the nominal IF (eg. pretuned or automatically tuned) and in which the signal properties are such that the portion used for detection (eg. the preamble) contains one of each possible symbol in N symbols (ie. at most Nxe2x88x921 consecutive ones or zeros in the 2-level GFSK modulation case).
FIG. 1 shows a conventional FM demodulator. The demodulated signal is obtained by firstly multiplying the incoming signal VIF by its time derivative, obtained from a differentiation circuit 3, in a multiplier 2. This operation makes the product amplitude proportional to the signal amplitude as well as the signal""s angular frequency (intermediate frequency plus FM frequency deviation). If the FM signal is held to a constant amplitude by means of automatic gain control (AGC) or use of a hard limiter, the product signal will have an amplitude proportional to the frequency deviation. Thus, the modulation signal can be easily recovered by feeding the multiplier output to a low-pass filter 1, to remove signal components at multiples of the IF frequency.
FM demodulators of this kind require accurate delay elements and filters with accurately controlled phase characteristics to generate the time-derivative approximation. Otherwise, excessive DC offsets will occur. Another source of DC offset is reference oscillator (LO) inaccuracies which result in the IF frequency being offset from its nominal value (hence corresponding to a DC level in the modulated FM signal).
Known IF filters and FM detectors in use today often employ passive resonator components that are trimmed, either at production or by exploiting signal properties. When the resonators are pre-tuned, they are tuned to the nominal IF frequency. FM detectors often exploit signal properties (e.g. notional zero mean of the detected signal) to automatically compensate for detuning. This detuning may be due to resonators deviating from their nominal values, or the received IF signal being offset in frequency due to a combination of frequency offsets in the local and remote reference oscillators.
Adjusting an IF strip (IF filter and FM detector) to the nominal IF frequency does not guarantee a DC free baseband signal, even if the baseband signal nominally has a zero mean. Skewing the detector of a properly tuned IF strip to minimize its DC offset will compensate for local and remote reference frequency differences and will improve sensitivity. Such FM detector offset compensation schemes rely on the signal having a theoretical zero mean (analog systems) or a known part of the signal (i.e. the preamble of a digital FM signal) having a theoretical zero mean. If the signal, or its preamble, is not so structured as to have zero mean, offset compensation is difficult and requires complex digital signalling processing (DSP) rather than simpler analog circuitry.
The present invention seeks to overcome these disadvantages by having a DC offset compensation circuit that does not rely on a signal having zero mean, or rely on a signal preamble having a zero mean, and which does not require complex digital signalling processing (DSP).
According to a first aspect of the invention, there is provided a frequency modulated signal demodulator including DC offset compensation, wherein the DC offset compensation circuit comprises means for deriving the positive and negative peak values of a frequency demodulated signal, means for determining the mean of the positive and negative peak values as an estimate of a DC offset value, and means for utilising this estimated DC offset value to compensate for DC offset in the frequency demodulated signal.
In a first preferred embodiment, a DC offset compensation circuit for use in an FM demodulator according to the invention comprises an input for receiving the frequency demodulated baseband signal; an output for an estimated DC offset signal; a pair of diodes connected in parallel with opposite polarity, between the input and output; a resistor connected in parallel with the pair of diodes; and, an output capacitor connected between the output and a ground terminal.
According to a second preferred embodiment, a DC offset compensation circuit for use in an FM demodulator according to the invention comprises an input for receiving a frequency demodulated signal; an output for an estimated DC offset signal; a first diode having its cathode connected to the input and its anode connected to a ground terminal via a first capacitor, wherein the anode is also connected to a negative supply terminal via a first resistor and to the output via a second resistor; a second diode having its anode connected to the input and its cathode connected to a ground terminal via a second capacitor, wherein the cathode is also connected to a positive supply terminal via a third resistor and to the output via a fourth resistor; and, a third capacitor connected between the output and a ground terminal.
Preferably, signal strength signal operated means is used to switch the peak signal offset compensation ON and OFF. This has the advantage of allowing the tracking to be switched ON when the signal strength is high and switched OFF when signals are weak, leading to faster settling time of the offset compensation circuit.
Preferably, the output of the envelope detector is passed to a filter for suppressing noise and other high-frequency components.
Preferably, the filter is a non-linear offset estimator. This has the advantage of speeding up the response at the turn on transient.